The present invention relates to a semiconductor device which is applicable to a delay inverter circuit for FinFET, for example.
Aiming at suppressing the short channel effect in association with micronization, WO2006/132172 proposes the field effect transistor (hereinafter referred to as fin type field effect transistor, FinFET for short) which is configured to have a projection semiconductor layer projecting upward from a substrate plane, and form a channel region on both planes (both side surfaces) substantially perpendicular at least to the substrate plane of the projection semiconductor layer. The FinFET is produced by forming the three-dimensional structure on the two-dimensional substrate. The gate volume of the FinFET will be larger than that of the planar typo transistor so long as the substrate has the same area. As the gate is configured to “envelope” the channel, the resultant channel controllability of the gate is high, and the leak current in the state where the device is in OFF state may be significantly reduced. Therefore, the threshold voltage may be set to be lower, resulting in optimum switching speed and energy consumption.